Planar superstrate CuInS2 (CIS) solar cell devices are fabricated using totally solution-processed deposition methods. A titanium dioxide blocking layer and an In2S3 buffer layer are deposited by the spray pyrolysis method. A CIS2 absorber layer is deposited by the spin coating method using CIS ink prepared by a 1-butylamine solvent-based solution at room temperature. To obtain optimum annealing temperature, these layers are first annealed at 150°C and then annealed at 210°C, 250°C and 350°C respectively. The optimum annealing temperature of the layer is found to be 250°C, where 23 mA current density and 505 mV open circuit voltage are measured for the best fabricated solar cell sample.